The present invention relates to a semiconductor device having a super junction structure and electrostatic discharge protection element, and a manufacturing method of the same.
A vertical DMOSFET (Double-diffused Metal Oxide Semiconductor Field Effect Transistor) is commonly known as a high withstand voltage power device for use in high withstand voltage power electronics applications. The vertical DMOSFET provides high withstand voltage thanks to the vertical thickness (depth) of a first conductivity type drift region and the impurity concentration.
For example, a so-called super junction structure is available as a vertical DMOSFET device structure which achieves compatibility between element withstand voltage and low Ron. In this structure, two types of regions, i.e., a first conductivity type drift region and second conductivity type pillar region, are alternately repeated (refer, for example, to Japanese Patent Laid-Open Nos. 2007-335844, 2008-4643, 2008-16518 and 2008-16562).
FIG. 7 illustrates a sectional structural diagram of a vertical DMOSFET having a super junction structure as an example of a semiconductor device of the past. In FIG. 7, a main body transistor (Tr) region 50 and ESD (Electrostatic Discharge) protection element region 60 in a vertical DMOSFET are shown both of which have a super junction structure.
A drift region 52 which includes a first conductivity type (n type) semiconductor region is formed on the main surface of a drain region 51. The drain region 51 includes a first conductivity type semiconductor region having a high impurity concentration (n+ type).
Second conductivity type (p type) pillar regions 53 are formed in the drift region 52. The same regions 53 are arranged periodically in the direction approximately parallel to the main surface of the drain region 51. The drift region 52 and pillar regions 53 form a so-called super junction structure. That is, the drift region 52 and pillar regions 53 are adjacent to each other to form p-n junctions.
Body regions 54 are formed on and in contact with the pillar regions 53. The body regions 54 each include a second conductivity type (p type) semiconductor region. As with the pillar regions 53, the body regions 54 are adjacent to the first conductivity type drift region to form p-n junctions.
Further, a gate insulating film 58 is provided on the drift region 52 and body regions 54.
In the main body Tr region 50, gate electrodes 57 are formed on the gate insulating film 58 in such a manner as to straddle a part of the body regions 54 and a part of the drift region 52.
Further, on the surfaces of the body regions 54, source regions 55 are selectively formed where the end portions of the gate electrodes 57 and those of the source regions 55 overlap each other. The source regions 55 each include a first conductivity type semiconductor region. Still further, on the surfaces of the body regions 54, potential extraction regions (backgates) 56 adapted to extract the potentials of the body regions 54 are formed, each adjacent to the source region 55. The potential extraction regions 56 each include a second conductivity type semiconductor region.
In the ESD protection element region 60, source regions 61 are selectively formed on the surfaces of the body regions 54. The source regions 61 each include a first conductivity type semiconductor region. Further, on the surfaces of the body regions 54, potential extraction regions (backgates) 62 adapted to extract the potentials of the body regions 54 are formed, each with a given spacing from the source region 61. The potential extraction regions 62 each include a second conductivity type semiconductor region.
An input terminal 63 is provided to ensure that the gate electrodes 57 of the main body Tr region 50 and the source regions 61 of the ESD protection element region 60 are at the same potential.
When a voltage is applied from the input terminal 63 to the gate electrodes 57, channel regions are formed in the body regions 54 immediately under the gate electrodes 57 between the source regions 55 and drift region 52. This causes electrons to move from the source regions 55 to the drift region 52. A current flow through the substrate as electrons move to the drift region 52 and then to the drain region 51.
In the vertical DMOSFET configuration shown in FIG. 7, the second conductivity type pillar regions 53 and first conductivity type drift region 52 have the same impurity concentration. This causes the pillar regions 53 and drift region 52 to be completely depleted when a reverse bias is applied between the drain and source with the transistor turned off, thus providing a uniform electric field distribution.
The semiconductor configuration shown in FIG. 7, therefore, provides high withstand voltage even if the impurity concentration of the drift region 52 is increased greater than when a super junction structure is not used. Further, because the impurity concentration of the drift region can be increased, a resistance Ron with the transistor turned on can be reduced. Thus, the semiconductor device configured as described above achieves compatibility between high element withstand voltage and low Ron.